ST70135 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST70135' PDF : 29 Pages View PDF
ST70135A
BitStream Interface
The Bitstream interface is a proprietary point to
point interface. The ST70135A is the bus master
of the interface. The interface is synchronous, a
common clock is used.
SLAP (Synchronous Link Access Protocol)
Interface
The SLAP interface is a point to point bitstream
interface. The ST70135A is the bus master of the
interface. The interface is synchronous, a
common clock (SLAP_CLOCK) is used. The basic
idea is illustrated in Figure 17.
The SLAP interface dumps the data of the fast
and interleaved channels on 2 separate sub
interfaces.
The data flow from the SLAP interface must be
enabled by the Transceiver Controller. A disabled
cell interface does not dump data on its interface.
Figure 18 : Common Clock Data Transfer
Source D Q
Rising
Clock
CK QN
DQ
Falling
Clock
CK QN Sink
Receive SLAP Interface
The interface signals use 2 signal types: (refer to
Figure 19)
– SLR_DATA [1:0]: data pins, a byte is transferred
in 4 cycles of 2 bits. The msb are transmitted
first, odd bits are asserted on SLR_DATA [1].
– SLR_VAL: indicates the data transfer and the
byte boundary
– SLR_FRAME: indicates the start of a super-
frame
Notice 2 SLAP interfaces are supported, one for
the fast data flow, the other one for the interleaved
data flow.
The logic timing diagram is shown in Figure 20.
Figure 19 : Receive Path, SLAP Interface
EXTERNAL
COMPONENT
(SLAVE)
DATA 2
VALID
FRAME
MODEM
(MASTER)
SLAP_CLOCK
Figure 20 : Receive SLAP Interface Timing
STM_CLOCK
FRAME
0
1
2
3
8
Minimum 8 cycles
Undefined
VALID
SLR_DATA(1)
SLR_DATA(0)
b7 b5 b3 b1
One byte as 4 times 2 bits
b6 b4 b2 b0
SLAP_CLOCK
Undefined
SLR_VAL must not repeat
in a 8 clock period
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