ST72124J View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72124J
STMicroelectronics
'ST72124J' PDF : 153 Pages View PDF
ST72334J/N, ST72314J/N, ST72124J
DATA EEPROM (Cont’d)
2.6.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
IE LAT PGM
Bit 7:3 = Reserved, forced by hardware to 0.
Bit 2 = IE Interrupt enable
This bit is set and cleared by software. It enables the
Data EEPROM interrupt capability when the PGM
bit is cleared by hardware. The interrupt request is
automatically cleared when the software enters the
interrupt routine.
0: Interrupt disabled
1: Interrupt enabled
Bit 1 = LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if PGM bit is cleared.
0: Read mode
1: Write mode
Bit 0 = PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is clearedby hardware and an interrupt is generated
if the ITE bit is set.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the PGM bit is cleared during the program-
ming cycle, the memory data is not guaranteed.
Table 3. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
EECSR
002Ch
Reset Value
0
0
0
0
IE
RWM
PGM
0
0
0
0
20/125
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