ST72334J/N, ST72314J/N, ST72124J
RESET SEQUENCE MANAGER (Cont’d)
Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 18.
Figure 18. Watchdog RESET Sequence
VDD
VDDnominal
VLVDf
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least tDELAYmin.
RUN
DELAY
RESET
INTERNAL RESET FETCH
4096 CLOCK CYCLES VECTOR
tDE LAYmin
RUN
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG UNDERFLOW
WATCHDOG RESET
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