ST72311
Table 6. Interrupt Mapping
Source
Block
RESET
TRAP
EI0
EI1
EI2
EI3
SPI
TIMER A
TIMER B
SCI
Description
Reset
Software
NOT USED
NOT USED
Ext. Interrupt (Ports PA0:PA3)
Ext. Interrupt (Ports PF0:PF2)
Ext. Interrupt (Ports PB0:PB3)
Ext. Interrupt (Ports PB4:PB7)
NOT USED
Transfer Complete
Mode Fault
Input Capture 1
Output Compare 1
Input Capture 2
Output Compare 2
Timer Overflow
Input Capture 1
Output Compare 1
Input Capture 2
Output Compare 2
Timer Overflow
Transmit Buffer Empty
Transmit Complete
Receive Buffer Full
Idle Line Detect
Overrun
NOT USED
NOT USED
NOT USED
Register
Label
N/A
N/A
Flag
N/A
N/A
N/A
N/A
N/A
N/A
SPISR
TASR
TBSR
SCISR
N/A
N/A
N/A
N/A
SPIF
MODF
ICF1_A
OCF1_A
ICF2_A
OCF2_A
TOF_A
ICF1_B
OCF1_B
ICF2_B
OCF2_B
TOF_B
TDRE
TC
RDRF
IDLE
OR
Exit
from
HALT
yes
no
yes
Vector
Address
Priority
Order
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
Highest
Priority
FFECh-FFEDh
FFEAh-FFEBh
no
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Lowest
Priority
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