ST72321M6 ST72321M9
POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
Active-halt and Halt modes are the two lowest
power consumption modes of the MCU. They are
both entered by executing the ‘HALT’ instruction.
The decision to enter either in Active-halt or Halt
mode is given by the MCC/RTC interrupt enable
flag (OIE bit in MCCSR register).
MCCSR Power Saving Mode entered when HALT
OIE bit
instruction is executed
0 Halt mode
1 ACTIVE-HALT mode
8.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see section
9.2 on page 53 for more details on the MCCSR
register).
The MCU can exit Active-halt mode on reception
of an MCC/RTC interrupt or a RESET. When exit-
ing Active-halt mode by means of an interrupt, no
256 or 4096 CPU cycle delay occurs. The CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 26).
When entering Active-halt mode, the I[1:0] bits in
the CC register are forced to ‘10b’ to enable inter-
rupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In Active-halt mode, only the main oscillator and its
associated counter (MCC/RTC) are running to
keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
The safeguard against staying locked in Active-
halt mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering Active-halt mode while the Watchdog is
active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
CAUTION: When exiting Active-halt mode follow-
ing an MCC/RTC interrupt, OIE bit of MCCSR reg-
ister must not be cleared before tDELAY after the
interrupt occurs (tDELAY = 256 or 4096 tCPU delay
depending on option byte). Otherwise, the ST7 en-
ters HALT mode for the remaining tDELAY period.
Figure 25. Active-halt Timing Overview
ACTIVE 256 OR 4096 CPU
RUN HALT CYCLE DELAY 1)
RUN
HALT
INSTRUCTION
[MCCSR.OIE=1]
RESET
OR
INTERRUPT
FETCH
VECTOR
Figure 26. Active-halt Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=1)
OSCILLATOR
PERIPHERALS 2)
CPU
I[1:0] BITS
ON
OFF
OFF
10
N
RESET
N
INTERRUPT 4)
Y
OSCILLATOR
ON
Y
PERIPHERALS
OFF
CPU
ON
I[1:0] BITS
XX 3)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 3)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. This delay occurs only if the MCU exits Active-
halt mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
4. In Flash devices only the MCC/RTC interrupt
can exit the MCU from Active-halt mode.
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