ST72331N4 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72331N4

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 256 EEPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS

STMicroelectronics 

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ST72E331 ST72T331

EEPROM (Cont’d)

5.2.3 Functional description

5.2.3.1 Read operation (E2LAT=0)

The EEPROM can be read as a normal ROM loca-

tion when the E2LAT bit of the CR register is

cleared. In a read cycle, the desired byte is put on

the data bus in less than 1 CPU clock cycle. This

means that reading data from EEPROM takes the

same time as reading data from EPROM, but this

memory cannot be used to execute machine code.

5.2.3.2 Write operation (E2LAT=1)

The EEPROM programming flowchart is shown in

Figure 24.

To access write mode set the E2LAT bit, the

E2PGM bit stays cleared. Then when a write ac-

cess to the EEPROM occurs, the value on the data

bus is latched on the 16 data latches depending

on the address.

When E2PGM is set, all the previous bytes written

(1 up to 16) are programmed in the EEPROM

cells. The effective high address (row) is deter-

mined by the last EEPROM write sequence. To

avoid wrong programming, the user must take

care that all the bytes written between two pro-

gramming sequences have the same high ad-

dress: only the four Least Significant Bits of the ad-

dress can change.

At the end of the cycle, the E2PGM and E2LAT

bits are cleared simultaneously, and an interrupt is

generated if the E2ITE bit is set.

Note: Care should be taken during the program-

ming cycle. Writing to the same memory location

will over-program the memory (logical AND be-

tween the two write access data result) because

the data latches are only cleared at the end of the

programming cycle and by the falling edge of

E2LAT bit.

It is not possible to read the latched data.

5.2.3.3 EEPROM Access Error handling

If a read access occurs while E2LAT=1, then the

data bus will not be driven.

If a write access occurs while E2LAT=0, then the

data on the bus will not be latched.

If a programming cycle is interrupted (by software/

RESET action), the memory data will not be guar-

anteed.

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