ST72361 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST72361' PDF : 224 Pages View PDF
ST72361
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example, in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 11.
For more details, refer to dedicated parametric
section.
Main features
■ Optional PLL for multiplying the frequency by 2
■ Reset Sequence Manager (RSM)
■ Multi-Oscillator Clock Management (MO)
– 4 Crystal/Ceramic resonator oscillators
■ System Integrity Management (SI)
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an fOSC2 of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then fOSC2 = fOSC/2.
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 187.
Figure 10. PLL Block Diagram
PLL x 2
fOSC
/2
0
fOSC2
1
PLL OPTION BIT
Figure 11. Clock, Reset and Supply Block Diagram
/ 8000
8-BIT TIMER
OSC2
OSC1
RESET
MULTI-
OSCILLATOR
(MO)
fOSC
fOSC2
PLL
(option)
SYSTEM INTEGRITY MANAGEMENT
MAIN CLOCK
CONTROLLER
WITH REALTIME
CLOCK (MCC/RTC)
fCPU
RESET SEQUENCE
MANAGER
(RSM)
AVD Interrupt Request
SICSR
0
AVD AVD LVD
IE F RF
0
0
0
WDG
RF
WATCHDOG
TIMER (WDG)
LOW VOLTAGE
VSS
DETECTOR
VDD
(LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
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