ST72361 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST72361' PDF : 224 Pages View PDF
ST72361
INTERRUPTS (Cont’d)
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the ISxx bits in the EICR register (Figure 21). This
control allows up to four fully independent external
interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
■ Falling edge
■ Rising edge
Figure 21. External Interrupt Control Bits
PORT A [7:0] INTERRUPTS
PAOR.0
PADDR.0
PA0
EICR
IS00 IS01
SENSITIVITY
CONTROL
■ Falling and rising edge
■ Falling edge and low level
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared by writing a dif-
ferent value in the ISx[1:0] of the EICR.
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
ei0 INTERRUPT SOURCE
PORT B [5:0] INTERRUPTS
PBOR.0
PBDDR.0
PB0
EICR
IS10 IS11
SENSITIVITY
CONTROL
AWUFH
Oscillator
/ AWUPR
To Timer Input Capture 1
PB0
PB1
PB2
ei1 INTERRUPT SOURCE
PB3
PB4
PB5
PORT C [2:1] INTERRUPTS
PCOR.7
PCDDR.7
PC1
EICR
IS20 IS21
SENSITIVITY
PC1
CONTROL
PC2
PORT D [7:6, 4, 1:0] INTERRUPTS
EICR
PDOR.0
PDDDR.0
PD0
IS30 IS31
SENSITIVITY
PD0
PD1
CONTROL
PD4
PD6
PD7
ei2 INTERRUPT SOURCE
ei3 INTERRUPT SOURCE
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