ST72621J2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST72621J2

LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI

STMicroelectronics 

Prev 21 22 23 24 25 26 27 28 29 30 Next

ST7262

Figure 18. Reset Timing Diagram

VDD

tDDR

OSCIN

fCPU

tOXOV

PC

RESET

FFFE FFFF

514 CPU

CLOCK

CYCLES

DELAY

Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+ and VIT-.

Figure 19. Reset Block Diagram

VDD

RESET

RON

200ns

Filter

tw(RSTL)out + 128 fOSC

delay

PULSE

GENERATOR

INTERNAL

RESET

WATCHDOG RESET

LVD RESET

Note: The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.

Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

22/132

Share Link: