ST72F324J2B6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72F324J2B6
STMicroelectronics
'ST72F324J2B6' PDF : 156 Pages View PDF
ST72324J/K
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 11.
For more details, refer to dedicated parametric
section.
Main features
s Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
s Reset Sequence Manager (RSM)
s Multi-Oscillator Clock Management (MO)
– 5 Crystal/Ceramic resonator oscillators
– 1 External RC oscillator
– 1 Internal RC oscillator
s System Integrity Management (SI)
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supplyClock
Security System (CSS) with Clock Filter and
Backup Safe Oscillator (enabled by option
byte)
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an fOSC2 of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then fOSC2 = fOSC/2.
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 127.
Figure 10. PLL Block Diagram
fOSC
PLL x 2
/2
0
fOSC2
1
PLL OPTION BIT
Figure 11. Clock, Reset and Supply Block Diagram
OSC2
OSC1
SYSTEM INTEGRITY MANAGEMENT
MULTI-
OSCILLATOR
(MO)
fOSC
fOSC2
PLL
(option)
CLOCK SECURITY SYSTEM
(CSS)
CLOCK
FILTER
SAFE
OSC
fOSC2
MAIN CLOCK
CONTROLLER
WITH REALTIME
fCPU
CLOCK (MCC/RTC)
RESET
VSS
VDD
RESET SEQUENCE
MANAGER
(RSM)
AVD Interrupt Request
SICSR
0
AVD AVD LVD
IE F RF
0
CSS CSS WDG
IE D RF
WATCHDOG
TIMER (WDG)
CSS Interrupt Request
LOW VOLTAGE
DETECTOR
(LVD)
AUXILIARY VOLTAGE
DETECTOR
(AVD)
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