ST72P314J2T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72P314J2T
STMicroelectronics
'ST72P314J2T' PDF : 153 Pages View PDF
ST72334J/N, ST72314J/N, ST72124J
MISCELLANEOUS REGISTERS (Cont’d)
6.2.3 Miscellaneous Registers Description
MISCELLANEOUS REGISTER 1 (MISCR1)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS
Bit 7:6 = IS1[1:0] EI2 and EI3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
EI2 (port B3..0) and EI3 (port B7..4). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).
IS11 IS10
External Interrupt Sensitivity
0 0 Falling edge & low level
0 1 Rising edge only
1 0 Falling edge only
1 1 Rising and falling edge
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled
(I/O pin free for general-purpose I/O)
1: MCO alternate function enabled
(fOSC/2 on I/O port)
Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.
Bit 4:3 = IS2[1:0] EI0 and EI1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:-
EI0 (port A3..0) and EI1 (port F2..0). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).
Bit 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
CP1
0
1
0
1
CP0
0
0
1
1
fOSC / 4
fOSC / 8
fOSC / 16
fOSC / 32
fCPU in SLOW mode
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC / 2
1: Slow mode. fCPU is given by CP1, CP0
See low power consumption mode and MCC
chapters for more details.
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