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ST72P361K9T3 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'ST72P361K9T3' PDF : 224 Pages View PDF
ST72361
POWER SAVING MODES (Cont’d)
Figure 27. ACTIVE HALT Timing Overview
RUN
ACTIVE
HALT
256 OR 4096 CYCLE
DELAY (AFTER RESET)
RUN
RESET
HALT
INSTRUCTION
OR
INTERRUPT
(Active Halt enabled)
FETCH
VECTOR
Figure 28. ACTIVE HALT Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=1)
(AWUCSR.AWUEN=0)
OSCILLATOR ON
PERIPHERALS 2)OFF
CPU
OFF
I[1:0] BITS
10
N
RESET
N
Y
INTERRUPT 3)
OSCILLATOR ON
Y
PERIPHERALS OFF
CPU
ON
I[1:0] BITS
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. This delay occurs only if the MCU exits ACTIVE
HALT mode by means of a RESET.
2. Peripheral clocked with an external clock
source can still be active.
3. Only the RTC interrupt and some specific inter-
rupts can exit the MCU from ACTIVE HALT
mode (such as external interrupt). Refer to
Table 9, “Interrupt Mapping,” on page 33 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits in the CC
register are set to the current software priority
level of the interrupt routine and restored when
the CC register is popped.
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