ST72T311R6T1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72T311R6T1
STMicroelectronics
'ST72T311R6T1' PDF : 164 Pages View PDF
ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
Table 6. Dedicated Interrupt Instruction Set
Instr uctio n
New Description
HALT
IRET
JRM
JRNM
POP CC
RIM
SIM
TRAP
WF I
Entering Halt mode
Interrupt routine return
Jump if I1:0=11
Jump if I1:0<>11
Pop CC from the Stack
Enable interrupt (level 0 set)
Disable interrupt (level 3 set)
Software trap
Wait for interrupt
F uncti on/Examp le
Pop CC, A, X, PC
I1:0=11 ?
I1:0<>11 ?
Mem => CC
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Software NMI
I1 H I0 N Z C
1
0
I1 H I0 N Z C
I1 H I0 N Z C
1
0
1
1
1
1
1
0
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current
software priority up to the next IRET instruction or one of the previously mentioned instructions.
In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never
be used in an interrupt routine.
Table 7. Interrupt Mapping
N°
Source
Block
Description
Register
Label
Priority
Order
Exit
from
HALT
Address
Vector
RESET
TRAP
Reset
Software Interrupt
Highest yes FFFEh-FFFFh
N/A
Priority no FFFCh-FFFDh
0
TLI
External Top Level Interrupt
MISCR2
yes FFFAh-FFFBh
1
MCC/RTC Main Clock Controller Time Base Interrupt MCCSR
FFF8 h-FFF9h
2
ei0
External Interrupt Port A3..0
FFF6 h-FFF7h
3
ei1
External Interrupt Port F2..0
N/A
4
ei2
External Interrupt Port B3..0
FFF4 h-FFF5h
FFF2 h-FFF3h
5
ei3
External Interrupt Port B7..4
FFF0 h-FFF1h
6
CAN
CAN Peripheral Interrupts
CANISR
FFEEh-FFE Fh
7
SPI
8
TIMER A
9
TIMER B
10
SCI
11
EEPROM
12
13 PWM ART
SPI Peripheral Interrupts
TIMER A Peripheral Interrupts
TIMER B Peripheral Interrupts
SCI Peripheral Interrupts
EEPROM Interrupt
Not Used
PWM ART Overflow Interrupt
SPISR
no FFECh-FFEDh
TASR
FFEA h-FFE Bh
TBSR
FFE8h-FFE 9h
SCISR
FFE6h-FFE 7h
EECSR
FFE4h-FFE 5h
Lowest
FFE2h-FFE 3h
ARTCSR Priority Yes FFE0h-FFE1h
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