ST75C520 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST75C520' PDF : 45 Pages View PDF
ST75C520
V.4 - Status - Reports
V.4.1 - Status
The ST75C520 has a dedicated status reporting
area located in its dual port RAM. This allow a
continuous monitoring of the status variables with-
out interrupting the ST75C520.
The first status byte gives the error status. Issuing
of an error status can also be flagged by a mask-
able interrupt for the controller. The signification of
the error codes are given in Chapter VII.
The second and third status bytes give the general
status of the modem. These status include for
example the ITU-T circuit status and other items
described in appendix. These two status can gen-
erate, when a change occurs, an interrupt to the
controller ; each bit of the two byte word can be
masked independently.
The forth byte gives in real time a measure of the
reception quality. This information may be used by
the controller to monitor the quality of the received
bits.
Three other locations are dedicated for custom
status reporting. The controller can program the
ST75C520 for a real time monitoring of any of its
internal RAM location. High byte or low byte of any
word can thus be monitored.
V.4.2 - Reports
The ST75C520 features an acknowledge and re-
port facility. The acknowledge of a command is
monitored by a counter COMACK located in the
dual port RAM. Each time a command is read from
the command area, the ST75C520 will increment
this counter. For instance, when a MR (Memory
Read) command is issued, the data is first written
in the report area, and the counter is incremented
afterwards. This way of processing insures data
integrity and gives additional synchronization be-
tween the controller and the data pump.
V.5 - Data Exchanges
The ST75C520 accepts many kinds of data ex-
change : the default mode uses the synchronous
serial exchange. Other modes include HDLC fram-
ing support and synchronous parallel exchanges.
Detailed description of the Data Buffer Exchanges
modes is available in the paragraph IX.
V.5.1 - Synchronous Parallel Mode
The data exchanges are made through the dual
port RAM and are byte synchronous oriented. The
double buffer facilities of the ST75C520 allow an
efficient buffering of the data.
V.5.1.1 - Transmit
Thecontrollermust firstfill at leastthe first bufferof data
(Tx Buffer 0) with the bits to be transmitted. In order to
perform this operation, the controller must first check
the Tx Buffer 0 status word DTTBS0. If this buffer is
empty, the controller fills the data buffer locations (up
to 64 bits), and then writes in DTTBS0 the number of
bytes contained in the buffer. The controller can then
either proceed with the second buffer or initiate the
transmission with a XMIT command.
The ST75C520 copies the contents of the data
buffer and then clears the buffer status word in
order to make it again available, then generates an
IT2 interrupt. The number of bytes specified by the
status word is then queued for transmission. The
process goes on with the two buffers until an XMIT
command stops the transmission. After the finish-
ing XMIT command has been issued, the last buff-
ers are emptied by the ST75C520.
Errors occur when both buffers are empty while the
transmit bit queue is also empty. Error is signalled
with an IT0 interruption to the controller.
V.5.1.2 - Receive
The controller should take care of releasing the Rx
buffers before the Data Carrier Detect goes true.
This is made by writing zero in the Rx Buffer Status
0 and 1. The ST75C520 then fills the first buffer,
and oncefilled sets the status word with the number
of bytes received and then generates an IT3 inter-
rupt. It then takes control of the second buffer and
operates the same way. The controller must check
the status of the buffers and empty them. Once the
data read, the controller must release the used
buffer and wait for the next buffer to be filled.
Error occurs when both buffers are declared full,
and incoming bits continue to arrive from the line.
Error is signaled by an IT0 interrupt.
V.5.2 - HDLC Parallel Mode
This mode implements part of the High Level Data
Link Control formats and procedures. It is well
suited for error correcting protocols like ECM or
FAX T4/T30 recommendations.It supports the flag-
ging generation,16-bit Frame Check Sequence,as
well as the Zero insertion/deletion mechanism.
V.5.3 - Serial Exchanges
The other mode of operation for data exchanges is
the Serial Synchronous Mode. In this mode, the
data I/O is made through the V.24 interface (page
4). Even when using the parallel mode described
above, the received bits are available on the
ST75C520 RxD Pin. See paragraph VII.2.1 table
for clock values.
17/45
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