ST75C530 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST75C530
SUPER INTEGRATED DEVICES WITH DSP, AFE & MEMORIES FORTELEPHONY, MODEM, FAX OVERINTERNET & POTS LINES
STMicroelectronics
'ST75C530' PDF : 84 Pages View PDF
ST75C530 - ST75C540
VI - USER INTERFACE (continued)
VI.4 - Status - Reports
VI.4.1 - Status
The ST75C530/540 has a dedicated status report-
ing area located in its dual port RAM. This allow a
continuous monitoring of the status variables with-
out interrupting the ST75C530/540.
The first status byte gives the error status. Issuing
of an error status can also be flagged by a mask-
able interrupt for the controller. The signification of
the error codes are given in Chapter VIII.
The second and third status bytes give the general
status of the modem. These status include for
example the ITU-T circuit status and other items
described in Chapter VIII “STATUS DESCRIP-
TION”. These two status can generate, when a
change occurs, an interrupt to the controller ; each
bit of the two byte word can be masked inde-
pendently.
The forth byte gives in real time a measure of the
receptionquality. Thisinformationmay be used by the
controller to monitor the quality of the received bits.
Four other locations are dedicated for custom
status reporting. The controller can program the
ST75C530/540 for a real time monitoring of any of
its internal RAM location. High byte or low byte of
any word can thus be monitored.
VI.4.2 - Reports
The ST75C530/540 features an acknowledge and
report facility. The acknowledge of a command is
monitored by a counter COMACK located in the
dual port RAM. Each time a command is read from
the command area, the ST75C530/540 will incre-
ment this counter. For instance, when a MR (Mem-
ory Read) command is issued, the data is first
written in the report area, and the counter is incre-
mented afterwards. This way of processinginsures
data integrity and gives additional synchronization
between the controller and the data pump.
VI.5 - Data Exchanges
The ST75C530/540 accepts many kinds of data
exchange: the defaultmode uses the synchronous
parallel exchange. Other modes include HDLC
framing support and UART. Detailed description of
the Data Buffer Exchanges modes is available in
the paragraph X.
VI.5.1 - Synchronous Parallel Mode
The data exchanges are made through the dual
port RAM and are byte synchronous oriented. The
double buffer facilities of the ST75C530/540 allow
an efficient buffering of the data.
VI.5.1.1 - Transmit
The controller must first fill at least the first buffer
of data (Tx Buffer 0) with the bits to be transmitted.
In order to perform this operation, the controller
must first check the Tx Buffer 0 status word
DTTBS0. If this buffer is empty, the controller fills
the data buffer locations (up to 64 bits), and then
writes in DTTBS0 the number of bytes contained in
the buffer. The controller can then either proceed
with the second buffer or initiate the transmission
with a XMIT command.
The ST75C530/540copies the contentsof the data
buffer and then clears the buffer status word in
order to make it again available, then generates an
IT2 interrupt. The number of bytes specified by the
status word is then queued for transmission. The
process goes on with the two buffers until an XMIT
command stops the transmission. After the finish-
ing XMIT command has been issued, the last buff-
ers are emptied by the ST75C530/540.
Errors occur when both buffersare empty while the
transmit bit queue is also empty. Error is signalled
with an IT0 interruption to the controller.
VI.5.1.2 - Receive
The controller should take care of releasing the Rx
buffers before the Data Carrier Detect goes true.
This is made by writing zero in the Rx Buffer Status
0 and 1. The ST75C530/540 then fills the first
buffer, and once filled sets the status word with the
number of bytes received and then generates an
IT3 interrupt. It then takes control of the second
buffer and operates the same way. The controller
must check the status of the buffers and empty
them. Once the data read, the controller must
release the used buffer and wait for the next buffer
to be filled.
Error occurs when both buffers are declared full,
and incoming bits continue to arrive from the line.
Error is signaled by an IT0 interrupt.
VI.5.2 - HDLC Parallel Mode
This mode implements part of the High Level Data
Link Control formats and procedures. It is well
suited for error correcting protocols like ECM or
FAXT4/T30 recommendations.It supportsthe flag-
ging generation,16-bit Frame Check Sequence,as
well as the Zero insertion/deletion mechanism.
VI.5.3 - UART Parallel Mode
This mode implement a 7 or 8 bit data format, it is
well suited for Caller ID or Minitel applications.
27/84
Share Link: 