ST7689
ST7689 I/O PIN ITO Resister Limitation
Pin Name
VDD, VDD1, VDD2~VDD5, VSS, VSS1, VSS2, VSS4, VD1IN, VD1OUT
V0IN, V0OUT, V0S ,XV0IN, XV0OUT ,XV0S , VgIN, VgOUT ,VgS ,Vm
VPP
A0, E_RD, RW_WR, /CS, D0 …D15, (SI), (SCL), TE
/RST
IF[3:1], CLS, /EXT, INTVD1
TCAP, CL, VREF
ITO Resister
<100Ω
<300Ω
<50Ω
<1KΩ
<10KΩ
<1KΩ
Floating
NOTE: 1. Make sure that the ITO resistance of COM0 ~ COM159 is equal, and so is it of SEG0 ~ SEG383. These limitations include the
bottleneck of ITO layout.
2. The ITO layout suggestion is shown as below:
Figure 2 Power ITO layout suggestion
Version 1.0
Page 28 of 195
2009/10