ST7FDALI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FDALI
STMicroelectronics
'ST7FDALI' PDF : 141 Pages View PDF
ST7DALI
12-BIT AUTORELOAD TIMER (Cont’d)
Bit 4 = BPEN Break Pin Enable.
This bit is read/write by software and cleared by
hardware after Reset.
0: Break pin disabled
1: Break pin enabled
INPUT CAPTURE REGISTER HIGH (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
15
8
Bit 3:0 = PWM[3:0] Break Pattern.
These bits are read/write by software and cleared
by hardware after a reset. They are used to force
the four PWMx output signals into a stable state
when the Break function is active.
PWMx DUTY CYCLE REGISTER HIGH (DCRxH)
Read / Write
Reset Value: 0000 0000 (00h)
15
8
0
0
0
0 DCR11 DCR10 DCR9 DCR8
PWMx DUTY CYCLE REGISTER LOW (DCRxL)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
Bits 15:12 = Reserved.
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. It defin-
esthe duty cycle of the corresponding PWM output
signal (see Figure 35).
In PWM mode (OEx=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWMx output signal (see Figure 35). In Output
Compare mode, they define the value to be com-
pared with the 12-bit upcounter value.
0
0
0
0 ICR11 ICR10 ICR9 ICR8
INPUT CAPTURE REGISTER LOW (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
7
0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bits 15:12 = Reserved.
Bits 11:0 = ICR[11:0] Input Capture Data.
This is a 12-bit register which is readable by soft-
ware and cleared by hardware after a reset. The
ATICR register contains captured the value of the
12-bit CNTR register when a rising or falling edge
occurs on the ATIC pin. Capture will only be per-
formed when the ICF flag is cleared.
TRANSFER CONTROL REGISTER (TRANCR)
Read/Write
Reset Value: 0000 0001 (01h)
7
0
0
0
0
0
0
0
0 TRAN
Bits 7:1 Reserved. Forced by hardware to 0.
Bit 0 = TRAN Transfer enable
This bit is read/write by software, cleared by hard-
ware after each completed transfer and set by
hardware after reset.
It allows the value of the DCRx registers to be
transferred to the DCRx shadow registers after the
next overflow event.
The OPx bits are transferred to the shadow OPx
bits in the same way.
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