ST7LITE0xY0, ST7LITESxY0
SUPPLY, RESET AND CLOCK MANAGEMENT (Cont’d)
Figure 14. Clock Management Block Diagram
CLKIN
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 RCCR
1MHz
Tunable
1% RC Oscillator
/2 DIVIDER
PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz
8MHz
4MHz
Option byte
0 to 8 MHz
fOSC
Option byte
fOSC /32 DIVIDER
7
8-BIT
LITE TIMER COUNTER
fLTIMER
(1ms timebase @ 8 MHz fOSC)
fOSC/32
1
fOSC
0
MCO SMS MCCSR
0
fCPU
TO CPU AND
PERIPHERALS
(except LITE
TIMER)
fCPU
MCO
26/124
1