ST7FLITE20 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE20
STMicroelectronics
'ST7FLITE20' PDF : 133 Pages View PDF
ST7LITE2
7.5 RESET SEQUENCE MANAGER (RSM)
7.5.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to section 12.2.1 on page 88 for further details.
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
■ Active Phase depending on the RESET source
■ 256 or 4096 CPU clock cycle delay (see table
below)
■ RESET vector fetch
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay is automatically select-
ed depending on the clock source chosen by op-
tion byte:
Clock Source
Internal RC Oscillator
External clock (connected to CLKIN pin)
External Crystal/Ceramic Oscillator
(connected to OSC1/OSC2 pins)
CPU clock
cycle delay
256
256
4096
Figure 15. Reset Block Diagram
VDD
The RESET vector fetch phase duration is 2 clock
cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of tSTARTUP (see
Figure 12).
Figure 14. RESET Sequence Phases
Active Phase
RESET
INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
7.5.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated RON weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least th(RSTL)in in
order to be recognized (see Figure 16). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
RESET
RON
Filter
PULSE
GENERATOR
INTERNAL
RESET
WATCHDOG RESET
ILLEGAL OPCODE RESET 1)
LVD RESET
Note 1: See “Illegal Opcode Reset” on page 88. for more details on illegal opcode reset conditions.
27/133
1
Share Link: 