ST7FLITE20 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE20
STMicroelectronics
'ST7FLITE20' PDF : 133 Pages View PDF
ST7LITE2
POWER SAVING MODES (Cont’d)
9.4 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when ACTIVE-HALT is disabled
(see section 9.5 on page 41 for more details) and
when the AWUEN bit in the AWUCSR register is
cleared.
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 35) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Fig-
ure 25).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes up im-
mediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see sec-
tion 15.1 on page 122 for more details).
Figure 24. HALT Timing Overview
RUN
HALT
256 OR 4096 CPU
CYCLE DELAY
RUN
RESET
OR
HALT
INTERRUPT
INSTRUCTION
[Active Halt disabled]
FETCH
VECTOR
Figure 25. HALT Mode Flow-chart
HALT INSTRUCTION
(Active Halt disabled)
(AWUCSR.AWUEN=0)
WDGHALT 1)
ENABLE
0
WATCHDOG
DISABLE
1
WATCHDOG
RESET
OSCILLATOR OFF
PERIPHERALS 2) OFF
CPU
OFF
I BIT
0
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR ON
PERIPHERALS OFF
CPU
ON
I BIT
X 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY5)
OSCILLATOR ON
PERIPHERALS ON
CPU
ON
I BIT
X 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 5 Interrupt Mapping for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when-
the CC register is popped.
5. If the PLL is enabled by option byte, it outputs
the clock after a delay of tSTARTUP (see Figure 12).
40/133
1
Share Link: 