ST7FLITE20 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE20
STMicroelectronics
'ST7FLITE20' PDF : 133 Pages View PDF
ST7LITE2
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
11.1.2 Main Features
■ Programmable free-running downcounter (64
increments of 16000 CPU cycles)
■ Programmable reset
■ Reset (if watchdog activated) when the T6 bit
reaches zero
Figure 33. Watchdog Block Diagram
■ Optional reset on HALT instruction
(configurable by option byte)
■ Hardware Watchdog selectable by option byte
11.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 16000 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
30µs.
RESET
WDGA T6
WATCHDOG CONTROL REGISTER (CR)
T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER
÷16000
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