INTERRUPTS (Cont’d)
Figure 20. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
FETCH NEXT INSTRUCTION
ST7LITE2
N
INTERRUPT
PENDING?
Y
N
EXECUTE INSTRUCTION
IRET?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt Mapping
N°
Source
Block
Description
Register
Label
Exit Exit
Priority from from
Order HALT or ACTIVE
AWUFH -HALT
Address
Vector
RESET Reset
TRAP Software Interrupt
0
AWU Auto Wake Up Interrupt
N/A Highest
Priority
AWUCSR
yes
no
yes1)
1
ei0
External Interrupt 0
2
ei1
External Interrupt 1
3
ei2
External Interrupt 2
N/A
yes
4
ei3
External Interrupt 3
5 LITE TIMER LITE TIMER RTC2 interrupt
LTCSR2
no
6
Not used
7
SI
AVD interrupt
SICSR
8
AT TIMER Output Compare Interrupt PWMxCSR
AT TIMER or Input Capture Interrupt
or ATCSR
9
AT TIMER Overflow Interrupt
ATCSR
no
10
LITE TIMER Input Capture Interrupt
LITE TIMER
11
LITE TIMER RTC1 Interrupt
LTCSR
LTCSR
12
SPI
SPI Peripheral Interrupts
13
Not usedNot used
SPICSR Lowest yes
Priority
Note 1: This interrupt exits the MCU from “Auto Wake-up from Halt” mode only.
yes FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
no FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
no
FFEAh-FFEBh
yes FFE8h-FFE9h
no FFE6h-FFE7h
yes FFE4h-FFE5h
no FFE2h-FFE3h
FFE0h-FFE1h
35/133
1