ST7LUS5, ST7LU05, ST7LU09
Register and memory map
Table 3. Hardware register map(1) (continued)
Address
Block Register label
Register name
Reset status Remarks
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h to
007Fh
DM(4)
DMCR
DMSR
DMBK1H
DMBK1L
DMBK2H
DMBK2L
DM control register
DM status register
DM breakpoint register 1 high
DM breakpoint register 1 low
DM breakpoint register 2 high
DM breakpoint register 2 low
Reserved area (47 bytes)
00h
R/W
00h
R/W
00h
R/W
00h
R/W
00h
R/W
00h
R/W
1. x = undefined, R/W = read/write
2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
t(s) 3. The bits associated with unavailable pins must always keep their reset value.
OObbssoolleettee PPrroodduucctt((ss)) -- OObbssoolleettee PPrroodduucct(s) 4. For a description of the DM registers, see the ST7 ICC Protocol Reference Manual.
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