ST7LUS5, ST7LU05, ST7LU09
Supply, reset and clock management
6.2.5 Clock controller control/status register (CKCNTCSR)
CKCNTCSR
7
6
5
Reserved
-
4
3
Reset value: 0000 1001 (09h)
2
1
0
AWU_FLAG
RC_FLAG
Reserved
RC/AWU
R/W
R/W
-
R/W
Table 11. CKCNTCSR register description
Bit
Name
Function
7:4
-
Reserved, must be kept cleared.
) AWU selection
t(s 3 AWU_FLAG This bit is set and cleared by hardware.
c 0: No switch from AWU to RC requested
u 1: AWU clock activated and temporization completed
d RC Selection
Pro t(s) 2
RC_FLAG
This bit is set and cleared by hardware.
0: No switch from RC to AWU requested
te c 1: RC clock activated and temporization completed
le du 1
-
Reserved, must be kept cleared.
so ro RC/AWU selection
b P 0
RC/AWU
0: RC enabled
- O te 1: AWU enabled (default value)
) le Table 12. Clock register map and reset values
t(s so Address Register
c b (Hex.)
label
7
6
5
rodu ) - O 0038h
MCCSR
Reset value
0
0
0
te P ct(s 0039h
RCCR
Reset value
CR9
1
CR8
1
CR7
1
sole rodu 003Ah
SICSR
Reset value
0
CR1
CR0
0
0
Ob P 003Eh
INTRCPRR
Reset value
CK2
0
CK1
0
CK0
0
Obsolete 003Fh
CKCNTCSR
Reset value
0
0
0
4
0
CR6
1
0
0
0
3
2
0
CR5
1
0
0
CR4
1
LVDRF
x
0
0
AWU_FLAG RC_FLAG
1
0
1
MCO
0
CR3
1
0
1
0
0
SMS
0
CR2
1
0
1
RC/AWU
1
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