ST7FLUS5MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLUS5MCE
STMicroelectronics
'ST7FLUS5MCE' PDF : 124 Pages View PDF
ST7LUS5, ST7LU05, ST7LU09
Central processing unit
Table 5. CC register description (continued)
Bit Name
Function
Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
3I
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I is
cleared. By default an interrupt routine is not interruptible because the I bit is set by
hardware at the start of the routine and reset by the IRET instruction at the end of the
routine. If the I bit is cleared by software in the interrupt routine, pending interrupts
) are serviced regardless of the priority level of the current interrupt routine.
t(s Negative
Product(s) 2 N
This bit is set and cleared by hardware. It is representative of the result sign of the
last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a
logic 1).
This bit is accessed by the JRMI and JRPL instructions.
lete uc Zero
- Obso te Prod 1 Z
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
t(s) ole Carry/borrow
s This bit is set and cleared by hardware and software. It indicates an overflow or an
c b underflow has occurred during the last arithmetic operation.
du - O 0 C
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
ro ) This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
P t(s instructions. It is also affected by the “bit test and branch”, shift and rotate
OObbssoolleettee Produc instructions.
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