ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7LITE20F2

8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, Timers, SPI

STMicroelectronics 

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Supply, reset and clock management

Figure 19. Using the AVD to monitor VDD

VDD

VIT+(AVD)

Early warning interrupt

(Power has dropped, MCU not

not yet in reset)

Vhyst

VIT-(AVD)

VIT+(LVD)

VIT-(LVD)

AVDF bit

0

AVD interrupt

request

if AVDIE bit = 1

LVD RESET

1

RESET

Interrupt cleared by

reset

1

0

Interrupt cleared by

hardware

7.6.3

Low power modes

Table 9.

Mode

Effect of low power modes on SI

Description

WAIT

HALT

No effect on SI. AVD interrupts cause the device to exit from WAIT mode.

The SICSR register is frozen. The AVD remains active.

Interrupts

The AVD interrupt event generates an interrupt if the corresponding enable control bit

(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

Table 10. Interrupt control bits

Interrupt event

Event flag

Enable control bit Exit from Wait Exit from Halt

AVD event

AVDF

AVDIE

Yes

No

Doc ID 8349 Rev 5

43/166

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