ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 166 Pages View PDF
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Electrical characteristics
13.3.2
Table 60. General operating conditions
Symbol
Parameter
Conditions
VDD Supply voltage
fCPU CPU clock frequency
fCPU = 4 MHz. max.
fCPU = 8 MHz. max.
3.3 V≤ VDD≤ 5.5 V
2.4 V≤ VDD<3.3 V
Min Max
2.4
5.5
3.3
5.5
up to 8
up to 4
Unit
V
MHz
Figure 52. fCPU maximum operating frequency versus VDD supply voltage
fCPU [MHz]
8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS OTHERWISE
STATED IN THE
TABLES OF
PARAMETRIC DATA)
4
2
0
2.0
2.4 2.7 3.3
3.5
4.0
SUPPLY VOLTAGE [V]
4.5
5.0
5.5
Operating conditions with low voltage detector (LVD)
TA = -40 to 85°C, unless otherwise specified
Table 61. Power on/power down operating conditions
Symbol
Parameter
Conditions
Min Typ Max Unit
VIT+(LVD)
Reset release threshold
(VDD rise)
VIT-(LVD)
Reset generation threshold
(VDD fall)
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
4.00(1) 4.25 4.50
3.40(1) 3.60 3.80
2.65(1) 2.90 3.15
V
3.80 4.05 4.30(1)
3.20 3.40 3.65(1)
2.40 2.70 2.90(1)
Vhys
VtPOR
LVD voltage threshold
hysteresis
VDD rise time rate (2)
tg(VDD) Filtered glitch delay on VDD
VIT+(LVD)-VIT-(LVD)
−
Not detected by the
LVD
−
200
−
mV
20
20000 μs/V
−
−
150 ns
IDD(LVD) LVD/AVD current consumption
−
−
220
−
μA
1. Not tested in production.
2. Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on
and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the
MCU.
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the
application, it is recommended to pull VDD down to 0 V to ensure optimum restart conditions. Refer to
circuit example in Figure 84: RESET pin protection when LVD is enabled
Doc ID 8349 Rev 5
121/166
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