ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 166 Pages View PDF
Supply, reset and clock management
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Figure 13. Clock management block diagram
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 RCCR
CLKIN
CLKIN
/OSC1
OSC2
Tunable
1% RC oscillator
fCPU
PLL
8 MHz -> 32 MHz
12-bit
at TIMER 2
Osc,PLLoff,
OSCRANGE[2:0]
Option bits
CLKIN
CLKIN
/2
divider
RC OSC
PLL 1 MHz -> 8 MHz
PLL 1 MHz -> 4 MHz
CLKIN/2
PLLx4x8
CLKIN/2
fOSC
OSC
1-16 MHZ
or 32 kHz
OSC /2
divider
OSC/2
fOSC /32 divider
8-bit
Lite timer 2 counter
fOSC/32
1
fOSC 0
Osc,PLLoff,
OSCRANGE[2:0]
Option bits
fLTIMER
(1ms timebase @ 8 MHz fOSC)
fCPU
To CPU and
peripherals
MCO SMS MCCSR
fCPU
MCO
7.4
Note:
Multi-oscillator (MO)
The main clock of the ST7 can be generated by four different source types coming from the
multioscillator block (1 to 16MHz or 32kHz):
● an external source
● 5 crystal or ceramic resonator oscillators
● an internal high frequency RC oscillator.
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 7.
Refer to Section 13: Electrical characteristics for more details.
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
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Doc ID 8349 Rev 5
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