ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 166 Pages View PDF
On-chip peripherals
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Note:
11.1.4
11.1.5
The application program must write in the CR register at regular intervals during normal
operation to prevent an MCU reset. This downcounter is freerunning: it counts down even if
the watchdog is disabled. The value to be stored in the CR register must be between FFh
and C0h (see Table 31: Watchdog timing):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset.
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
Table 31. Watchdog timing(1)
WDG counter code
fCPU = 8 MHz
min [ms]
max [ms]
C0h
1
2
FFh
127
128
1. The timing variation is due to the unknown status of the prescaler when writing to the CR register.
The number of CPU clock cycles applied during the reset phase (256 or 4096) must be
taken into account in addition to these timings.
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the CR is not used.
Refer to the Option Byte description in Section 15: Device configuration.
Using HALT mode or ACTIVE-HALT mode with the WDG (WDGHALT option)
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
Same behavior in active-halt mode.
Interrupts
None.
72/166
Doc ID 8349 Rev 5
Share Link: 