ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 166 Pages View PDF
On-chip peripherals
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Figure 40. Lite timer 2 block diagram
fOSC/32
LTCNTR
8-bit timebase
counter 2
LTCSR2
LTTB2
Interrupt request
0
0
0
0
0
0 TB2IE TB2F
8
LTARR
8-bit autoreload
register
fLTIMER To 12-bit AT TImer
LTIC
8-bit timebase
counter 1
8
LTICR
8-bit
Input capture
register
/2
1
fLTIMER
0 Timebase
1 or 2 ms
(@ 8MHz
fOSC)
LTCSR1
ICIE ICF TB TB1IE TB1F
LTTB1 interrupt request
LTIC interrupt request
11.3.3
Functional description
Timebase counter 1
The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of fOSC/32. An overflow event occurs when the
counter rolls over from F9h to 00h. If fOSC = 8 MHz, then the time period between two
counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the
LTCSR1 register.
When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is
generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1
register.
Input capture
The 8-bit input capture register is used to latch the free-running upcounter (Counter 1) 1
after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the
ICF bit is set and the LTICR1 register contains the MSB of Counter 1. An interrupt is
generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
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Doc ID 8349 Rev 5
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