ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
Central processing unit
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
Index registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective
addresses or temporary storage areas for data manipulation. The cross-assembler
generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.
The Y register is not affected by the interrupt automatic procedures (not pushed to and
popped from the stack).
Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (program counter high which is the MSB).
Condition code register (CC)
Read / Write
Reset value: 111x1xxx
7
0
1
1
1
H
I
N
Z
C
Note:
The 8-bit Condition Code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
● Bit 4 = H Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during
an ADD or ADC instruction. It is reset by hardware during the same instructions.
0: No half carry has occurred
1: A half carry has occurred
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
● Bit 3 = I Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled
1: Interrupts are disabled
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM
and JRNM instructions.
Interrupts requested while I is set are latched and can be processed when I is cleared. By
default an interrupt routine is not interruptible because the I bit is set by hardware at the start
of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared
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Doc ID 8349 Rev 5
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