ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 166 Pages View PDF
Power saving modes
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Figure 25. HALT mode flowchart
HALT instruction
(ACTIVE-HALT disabled)
(AWUCSR.AWUEN=0)
WDGHALT (1)
ENABLE
0
Watchdog
DISABLE
1
Watchdog
reset
Oscillator
Peripherals (2)
CPU
I bit
OFF
OFF
OFF
0
N
Reset
N
Y
Interrupt (3)
Y
Oscillator
ON
Peripherals
OFF
CPU
ON
I bit
X 4)
256 or 4096 CPU clock
cycle delay(5)
Oscillator
ON
Peripherals
ON
CPU
ON
I bit
X 4)
Fetch reset vector
or service interrupt
9.4.1
1. WDGHALT is an option bit (see Section 15.1: Option bytes for more details).
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to
Table 12: Interrupt mapping for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
5. If the PLL is enabled by option byte, it outputs the clock after a delay of tSTARTUP (see Figure 12: PLL
output frequency timing diagram).
HALT mode recommendations
● Make sure that an external event is available to wake up the microcontroller from Halt
mode.
● When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
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Doc ID 8349 Rev 5
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