ST72104G, ST72215G, ST72216G, ST72254G
INTERRUPTS (Cont’d)
Figure 15. Interrupt Processing Flowchart
FROM RESET
I BIT SET?
N
Y
FETCH NEXT INSTRUCTION
N
INTERRUPT
PENDING?
Y
N
EXECUTE INSTRUCTION
IRET?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt Mapping
N°
Source
Block
Description
RESET Reset
TRAP
Software Interrupt
0
ei0
External Interrupt Port A7..0 (C5..01)
1
ei1
External Interrupt Port B7..0 (C5..01)
2
CSS
Clock Security System Interrupt
3
SPI
SPI Peripheral Interrupts
4
TIMER A TIMER A Peripheral Interrupts
5
Not used
6
TIMER B TIMER B Peripheral Interrupts
7
Not used
8
Not used
9
Not used
10
Not used
11
I²C
I²C Peripheral Interrupt
12
Not Used
13
Note
Not Used
1. Configurable by option byte.
Register
Label
Priority
Order
Exit
from
HALT
Highest yes
Priority no
N/A
yes
CRSR
SPISR
no
TASR
TBSR
no
I2CSRx
no
Lowest
Priority
Address
Vector
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
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