ST8004 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST8004' PDF : 26 Pages View PDF
Functional description
ST8004
6.4
Clock circuitry
The clock signal (CLK) to the card is either derived from a clock signal input on the pin
XTAL1 or from a crystal up to 26 MHz connected between pins XTAL1 and XTAL2.
The frequency may be chosen at fXTAL,1/2 fXTAL,1/4 fXTAL or 1/8 fXTAL via pins CLKDIV1 and
CLKDIV2 (see Table 18.). The frequency change is synchronous, which means that during
transition, no pulse is shorter than 45% of the smallest period and that the first and last clock
pulse around the change has the correct width.
In the case of fXTAL, the duty factors depend on the signal at XTAL1.
In order to reach a 45% to 55% duty factor on the pin CLK the input signal on XTAL1 should
have a duty factor of 48% to 52% and transition times of less than 5% of the input signal
period.If a crystal is used with fXTAL, the duty factor on pin CLK may be 45% to 55%
depending on the layout and on the crystal characteristics and frequency. In the other cases,
it is guaranteed between 45% and 55% of the period. The crystal oscillator runs as soon as
the IC is powered-up. If the crystal oscillator is used, or if the clock pulse on XTAL1 is
permanent, then the clock pulse will be applied to the card according to the timing diagram
of the activation sequence. If the signal applied to XTAL1 is controlled by the micro-
controller, then the clock pulse will be applied to the card by the microcontroller after
completion of the activation sequence.
Table 18. Clock circuitry
CLKDIV1
0
0
1
1
CLKDIV2
0
1
1
0
CLK
1/8 fXTAL
1/4 fXTAL
1/2 fXTAL
fXTAL
6.5
I/O Circuitry
The three data lines I/O, AUX1 and AUX2 are identical. The Idle state is realized by data
lines I/O and I/OUC being pulled HIGH via a 10k resistor (I/O to VCC and I/OUC to VDD). I/O
is referenced to VCC, and I/OUC to VDD, thus allowing operation with VCC ≠ VDD. The first
line on which a falling edge occurs becomes the master. An anti-latch circuit disables the
detection of falling edges on the other line, which then becomes the slave. After a time delay
td (edge) (approximately 200 ns), the N transistor on the slave line is turned on, thus
transmitting the logic 0 present on the master line.When the master line returns to logic 1,
the P transistor on the slave line is turned on during the time delay td (edge) and then both
lines return to their idle state. This active pull-up feature ensures fast LOW-to-HIGH
transitions; it is able to deliver more than 1 mA up to an output voltage of 0.9 VCC on a 80pF
load. At the end of the active pull-up pulse, the output voltage only depends on the internal
pull-up resistor, and on the load current. The maximum frequency on these lines is 1MHz.
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