ST90135M6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST90135M6' PDF : 199 Pages View PDF
ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY SIGNALS (Cont’d)
7.2.4 RW: Read/Write
Note: On some devices, the internal weak pull-up
RW (Alternate Function Output, Active low,
Tristate) identifies the type of memory cycle:
is not present. In this case, an external one is
needed.
RW=”1” identifies a memory read cycle, RW=”0” The behavior of this signal is affected by the MC,
identifies a memory write cycle. It is defined at the ETO and BSZ bits in the EMR1 register. Refer to
beginning of each memory cycle and it remains the Register description.
stable until the following memory cycle. RW is re-
leased in high-impedance during bus acknowl-
edge cycle or under processor control by setting
the HIMP bit (MODER). RW is enabled via soft-
ware as the Alternate Function output of the asso-
7.2.5 BREQ, BACK: Bus Request, Bus
Acknowledge
Note: These pins are available only on some ST9
devices (see Pin description).
ciated I/O port bit (refer to specific ST9 device to BREQ (Alternate Function Input, Active low) indi-
identify the port and pin). Under Reset status, the cates to the ST9 that a bus request has tried or is
associated bit of the port is set into bidirectional
weak pull-up mode.
trying to gain control of the memory bus. Once en-
abled by setting the BRQEN bit (MODER.1,
R235), BREQ is sampled with the falling edge of
the processor internal clock during phase T2.
n
n
Figure 46. External memory Read/Write sequence with external wait (WAIT pin)
n
T1
T2
T1
T2
T1
T2
WAIT
SYSTEM
CLOCK
P1
AS (MC=0)
ALE (MC=1)
DS (MC=0)
MULTIPLEXED
P0
RW (MC=0)
DS (MC=1)
RW (MC=1)
MULTIPLEXED
P0
RW (MC=0)
DS (MC=1)
RW (MC=1)
ADDRESS
ADD.
D.IN
ADD. D.OUT
ADDRESS
ADDRESS
ADDRESS
D.IN
ADD.
D.IN
ADDRESS
D.OUT ADD.
DATA OUT
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