ST92F124/F150/F250 - INTERRUPTS
EXTERNAL INTERRUPTS (Contβd)
Figure 51. External Interrupt Control Bits and Vectors
INT 0 pin*
INT 1 pin*
INT 2 pin*
INT 3 pin*
Watchdog/Timer IA0S
End of count
TEA0
β0β
TEA1 STIM Timer
β1β
INTS
β0β
TEB0
β1β
EFTIS
EFT0 Timer
β1β
TEB1
β0β
EFTIS
EFT1 Timer
β1β
TEC0
β0β
FEIEN
E3 TM/Flash
VECTOR V7 V6 V5 V4 0 0 0 X
Priority level
XX 0
Mask bit IMA0
Pending bit IPA0
VECTOR V7 V6 V5 V4 0 0 1 X
Priority level
XX 1
Mask bit IMA1
Pending bit IPA1
VECTOR V7 V6 V5 V4 0 1 0 X
Priority level
XX 0
Mask bit IMB0
Pending bit IPB0
VECTOR V7 V6 V5 V4 0 1 1 X
Priority level
XX 1
Mask bit IMB1
Pending bit IPB1
INT 4 pin*
TEC1
INT 5 pin*
β1β
β0β
SPIS
SPI
β1β
β0β
VECTOR V7 V6 V5 V4 1 0 0 X
Priority level
XX 0
Mask bit IMC0
Pending bit IPC0
VECTOR V7 V6 V5 V4 1 0 1 X
Priority level
XX 1
Mask bit IMC1
Pending bit IPC1
INT 6 pin
TED0
RCCU
INT_SEL
β1β
β0β
VECTOR V7 V6 V5 V4 1 1 0 X
Priority level
XX 0
Mask bit IMD0
Pending bit IPD0
ID1S
NMI
WKUP
(0:15)
β1β
Wake-up
Controller
β0β
VECTOR V7 V6 V5 V4 1 1 1 X
Priority level
XX 1
Mask bit IMD1
Pending bit IPD1
INT A0
request
INT A1
request
INT B0
request
INT B1
request
INT C0
request
INT C1
request
INT D0
request
INT D1
request
* Only four interrupt pins are available. Refer to Table 19 for I/O pin mapping.
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