ST92R195B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST92R195B' PDF : 18 Pages View PDF
ST92R195B - ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS (Cont’d)
EXTERNAL MEMORY INTERFACE TIMING TABLE
(VDD= 5V +/-10%; TA= 0 to 70°C; unless otherwise specified))
Symbol
Parameter
Value
Unit
typ
max
TwDSR
DSN low level pulse width (read)
TpC*(1/2+WDS)-6
ns
TwDSW
DSN low level pulse width (write)
TpC*(1/2+WDS)-6
ns
TdDSR(DR) DSN↓ to data valid delay
TpC*(1/2+WDS)-16
ns
ThDR(DS)
Data to DSN↑ hold time
0
ns
TdDS(A)
DSN↑ to address active delay
TpC/2
ns
ThDS(AS)
DSN↑ to ASN↓ delay
TpC/2 + 6
ns
TsRW(AS) R/WN setup time before ASN↑
TpC*(1/2 + WAS) - 8
ns
TdDSR(RW) DSN↑ to R/WN and address not valid delay
TpC/2
ns
TdDW(DSW) Write data valid to DSN↓ delay (write)
0
ns
ThDS(DW) Data hold time after DSN↑ (write)
TpC/2
ns
TdA(DR)
Address valid to data valid delay (read)
T pC*(3/2+WDS+W AS)- 14
ns
TpC is the INTCLK clock period.
SPI TIMING TABLE
(VDD= 5V +/-10%; TA= 0 to 70°C; Cload= 50pF)
Symbol
TsDI
ThDI
TdOV
ThDO
TwSKL
TwSKH
Parameter
Input Data Set-up Time
Input Data Hold Time
(1)
SCK to Output Data Valid
Output Data Hold Time
SCK Low Pulse Width
SCK High Pulse Width
Conditi on
OSCIN/2 as internal Clock
Value
Unit
min
max
tbd
ns
1INTCLK +100ns ns
tbd
ns
tbd
ns
tbd
ns
tbd
ns
(1) TpC is the OSCIN clock period; TpMC is the “Main Clock Frequency” period.
SKEW CORRECTOR TIMING TABLE
(VDD= 5V +/-10%, TA= 0 to 70°C, unless otherwise specified)
Symbol
Parameter
Conditions
Tjskw
Jitter on RGB output
36 MHz Skew corrector clock frequency
max
Value
Unit
5*
ns
(*) The OSD jitter is measured from leading edge to leading edge of a single character row on consecutive TV lines. The value is an envelope
of 100 fields
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