STA011 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA011' PDF : 38 Pages View PDF
STA011
5
I2C-bus interface
I2C-bus interface
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
Data transmission from the microprocessor to the STA011 takes place through the 2 wires
(SDA and SCL) of the I2C-bus interface. The STA011 is always a slave device.
I2C-bus specifications
The I2C-bus protocol defines any device that sends data to the bus as a transmitter, and any
device that reads the data as a receiver. The device that controls the data transfer is known
as the Master and the others as the slave. The master will always initiate the transfer and
will provide the serial clock for synchronization.
Power ON reset
The device at Power ON is able to configure itself to a fixed configuration, with all the
circuitry ON and the RFPLL output frequency set to 1356.54MHz (fcomp=3.68MHz,
N=368.625)
Data validity
Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while
the clock is HIGH are used to identify START or STOP condition.
Start condition
Start is identified by a HIGH to LOW transition of the data bus SDA while the clock signal
SCL is stable in the HIGH state. A Start condition must precede any command for data
transfer.
Stop condition
A LOW to HIGH transition of the data bus SDA identifies a stop while the clock signal SCL is
stable in the HIGH state. A STOP condition terminates communications between the
STA011 and the Bus Master.
Byte format
Every byte transferred on the SDA line must contain bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
Acknowledge
An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either
master or slave, will release the SDA bus after sending 8 bits of data.
During the 9th clock pulse the receiver pulls the SDA low to acknowledge the receipt of 8
bits of data.
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