STA015 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA015' PDF : 44 Pages View PDF
STA015-STA015B-STA015T
5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0
BIT_EN
SCKR
t_biten
t_biten
tsckr_min_period
tsckr_min_low
tsckr_min_high
SCLK_POL=0
SDI
IGNORED
VALID
IGNORED
tsdi_setup
tsdi_hold
D98AU971A
5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1
BIT_EN
SCKR
SDI IGNORED
tsdi_setup_min = 2ns
tsdi_hold_min = 3ns
tsckr_min_hi = 10ns
tsckr_min_low = 10ns
tsckr_min_lperiod = 50ns
t_biten (min) = 2ns
t_biten
t_biten
tsckr_min_period
tsckr_min_low
tsckr_min_high
SCLK_POL=4
IGNORED
VALID
tsdi_setup
tsdi_hold
IGNORED
D99AU1038
5.4.3. SRC_INT
This is an asynchronous input used in "broadcast’ mode.
SRC_INT is active low
SRC_INT
t_src_hi
t_src_low
t_src_low min duration is 50ns (1DSP clock period)
t_src_high min duration is 50ns (1DSP clock period)
D98AU972
5.4.4. XTI,XTO and CLK_OUT timings
XTI (INPUT)
thi
tlo
XTO
txto
CLK_OUT
tclk_out
D98AU973
txto = 1.40 + pad_timing (Cload_XTO) ns
tclk_out = 4 + pad_timing (Cload_CLK_OUT) ns
Note: In "multimedia" mode, the CLK_OUT pad is DATA_REQ. In that case, no timing is given between the XTI input and this pad.
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