STA120 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA120' PDF : 15 Pages View PDF
STA120
Figure 4. Special Audio Port Formats 12 and 13
FSYNC(out)
LEFT
SCK(out)
SDATA(out)
AUX
LSB
MSB V U C P
RIGHT
AUX
LSB
MSB V U C P
FSYNC(out)
SCK(out)
SDATA(out)
LEFT
AUX
LSB
MSB V U C P
RIGHT
AUX
LSB
MSB V U C P
D98AU987
Error And Frequency Reporting
When SEL is low, error and received frequency information are selected.
The error information is encoded on pins E2, E1, and E0, and is decoded as shown in Table 3. When an
error occurs, the corresponding error code is latched.
Clearing is then accomplished by bringing SEL high for more than eight MCK cycles. The errors have a
priority associated with their error code, with validity having the lowest priority that occurred since the last
clearing will be selected.
Table 3. Error Decoding
E2
E1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Figure 5. CBL Timing
CBL
E0
Error
0
No Error
1
Validity Bit High
0
Confidence flag
1
Slipped Sample
0
CRC Error (PRO only)
1
Parity Error
0
Bi-Phase Coding Error
1
No Lock
C0
Ca-Ce
SDATA RIGHT 191
LEFT 0
RIGHT 0
LEFT 1 RIGHT 31 LEFT 32
RIGHT 191
LEFT 0
FSYNC
ERF,
VERF
C, U
D98AU988
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