STA304A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA304A' PDF : 30 Pages View PDF
STA304A
and read or write mode.
The 7 most significant bits are the device address identifier, corresponding to the I2C bus definition.
In STA304A the I2C interface has two device address depending on SA pin configuration 0011110 when SA =
0, and 0011111 when SA = 1.
The 8th bit (LSB) is the read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After
a START condition the STA304A identifies on the bus the device address and, if a match is found, it acknowl-
edges the identification on SDA bus during the 9th bit time. The following byte after the device identification byte
is the internal space address.
11.3 WRITE OPERATION
Following a START condition the master sends a device select code with the RW bit set to 0. The STA304A
acknowledges this and waits for the byte of internal address. After receiving the internal bytes address the
STA304A again responds with an acknowledge.
11.3.1Byte write
In the byte write mode the master sends one data byte, this is acknowledged by STA304A. The master then
terminates the transfer by generating a STOP condition.
11.3.2Multibyte write
The multibyte write mode can start from any internal address. The transfer is terminated by the master gener-
ating a STOP condition.
Figure 13. Write Mode Sequence
BYTE
WRITE
START
MULTIBYTE
WRITE
START
DEV-ADDR
DEV-ADDR
ACK
RW
ACK
RW
SUB-ADDR
ACK
SUB-ADDR
ACK
DATA IN
DATA IN
ACK
STOP
ACK
DATA IN
D98AU825B
ACK
STOP
Figure 14. Read Mode Sequence
CURRENT
ADDRESS
READ
START
RANDOM
ADDRESS
READ
START
SEQUENTIAL
CURRENT
READ
START
SEQUENTIAL
RANDOM
READ
START
ACK
DEV-ADDR
DEV-ADDR
RW
ACK
DEV-ADDR
RW
RW= ACK
HIGH
DEV-ADDR
ACK
RW
DATA
SUB-ADDR
DATA
NO ACK
STOP
ACK
DEV-ADDR
START
ACK
DATA
ACK
RW
ACK
SUB-ADDR
ACK
START
DEV-ADDR
ACK
RW
DATA
DATA
DATA
NO ACK
STOP
NO ACK
ACK
STOP
DATA
ACK
D98AU826A
DATA
NO ACK
STOP
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