STA308A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA308A' PDF : 63 Pages View PDF
STA308A
Registers
7.2
7.2.1
Register description
Configuration register A (0x00)
D7
COS1
1
D6
COS0
0
D5
DSPB
0
D4
IR1
0
D3
IR0
0
D2
MCS2
0
D1
MCS1
1
D0
MCS0
1
Bit
RW
RST
Name
Description
0
RW
1
1
RW
1
2
RW
0
MCS0
MCS1
MCS2
Master clock select: selects the ratio between the
input I2S sample frequency and the input clock.
The DDX8000 supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4
kHz, 192 kHz, and 2.8224 MHz DSD. Therefore the internal clocks are:
" 65.536 MHz for 32 kHz
" 90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD
" 98.304 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fs). The relationship between the input clock and the input sample rate is
determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits
determine the PLL factor generating the internal clock and the IRn bits determine the
oversampling ratio used internally.
Input sample rate
IR
fs (kHz)
32, 44.1, 48
00
88.2, 96
01
176.4, 192
10
DSD
11
Interpolation ratio select
1XX
128 * fs
64 * fs
64 * fs
2 * fs
011
256 * fs
128 * fs
128 * fs
4 * fs
MCS[2:0]
010
384 * fs
192 * fs
192 * fs
6 * fs
001
512 * fs
256 * fs
256 * fs
8 * fs
000
768 * fs
384 * fs
384 * fs
10 * fs
Bit RW RST
Name
Description
3
RW
0
IR0
4
RW
0
IR1
Interpolation ratio select: selects internal
interpolation ratio based on input I2S sample
frequency
The STA308A has variable interpolation (oversampling) settings such that internal
processing and DDX output rates remain consistent. The first processing block interpolates
by either 4 times, 2 times, or 1 time (pass-through).
The oversampling ratio of this interpolation is determined by the IR bits.
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