STA309B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA309B' PDF : 66 Pages View PDF
STA309B
Registers
7.2.4 Configuration register D (0x03)
D7
MPC
1
D6
CSZ4
1
D5
CSZ3
0
D4
CSZ2
0
D3
CSZ1
0
D2
CSZ0
0
D1
OM1
1
D0
OM0
0
Bit RW RST
Name
Description
0
RW
0
1
RW
1
OM0
OM1
FFX power output mode: selects configuration of
FFX output
The FFX power output mode selects how the FFX output timing is configured. Different
power devices use different output modes. The STA50x recommended use is
OM = 10.
OM[1,0]
00
01
10
11
Output stage - mode
STA50x/STA51xB - drop compensation
Discrete output stage - tapered compensation
STA50x/STA51xB - full power mode
Variable drop compensation (CSZn bits)
Bit RW
2
RW
3
RW
4
RW
5
RW
6
RW
RST
Name
0
CSZ0
0
CSZ1
0
CSZ2
0
CSZ3
1
CSZ4
Description
Contra size register: when OM[1,0] = 11, this register
determines the size of the FFX compensating pulse
from 0 clock ticks to 31 clock periods.
CSZ[4:0]
00000
00001
…
11111
Compensating pulse size
0 clock period compensating pulse size
1 clock period compensating pulse size
…
31 clock period compensating pulse size
Bit RW RST
Name
Description
7
RW
1
MPC
Max power correction: setting to 1 enables STA50x
correction for THD reduction near maximum power
output
Setting the MPC bit turns on special processing that corrects the STA50x power device at
high power. This mode should lower the THD+N of a full STA50x FFX system at maximum
power output and slightly below. This mode will only be operational at OM[1,0] = 01.
Doc ID 022570 Rev 2
27/66
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