STA310 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA310' PDF : 90 Pages View PDF
STA310
9.2 Register map by function
Code
Description
(a) Register modification is ALWAYS taken into account by the audio decoder.
Any change to these registers is taken into account immediately.
(b) Register modification is taken into account AFTER EVERY DECODED DATA BLOCK or JUST AFTER
RESET (soft or hard).
The decoded block is related to the granularity of the computation in the audio decoder software.
A block is 256 samples in Dolby Digital, 96 samples in MPEG, 80 samples in LPCM/PCM.
(f)
Register modification is taken into account AFTER EVERY DATA FRAME.
A frame is: 1152 samples in MPEG I/II, 1536 samples in Dolby Digital, 384 samples in MPEG-1 layer 1, 80
samples in LPCM/PCM.
(r)
Register modification is taken into account ONLY WHEN THE DSP IS RUN AFTER RESET (soft or hard).
(1) The delay registers are updated when bit 0 of the UPDATE register is set to 1.
(2) The volume is updated when CHAN_IDX is set to the appropriate value.
(3) The Karaoke mode is updated when KAR_UPDATE is set to ’1’.
The following tables list the register map by address and function, then each audio decoder register is described
individually
Table 8.
Register function
VERSION
SETUP + INPUTS
PCM CONFIGURATION
DAC AND PLL CONFIGURATION
HEX
0x00
0x01
0x71
0x0C
0x0D
0x54
0x55
0x56
0x05
0x12
0x18
0x0E
0x12
0x11
0x1D
0x12
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
DEC
0
1
113
12
13
84
85
86
5
18
24
14
18
17
29
18
181
182
183
184
185
186
187
188
189
190
Name
VERSION
IDENT
SOFT‘VER
SIN_SETUP (a)
CAN_SETUP (a)
PCMDIVIDER (b)
PCMCONF (b)
PCMCROSS (b)
SFREQ (f)
PLLCTRL (f)
PLLMASK (a)
DATA IN
PLLCTRL (f)
PLL_DATA (a)
PLL_CMD(f)
PLL_ADD (f)
ENA_ALL FRACPLL
AU_PLL_FRACL_192
AU_PLL_FRACH_192
AU_PLL_XDIV_192
AU_PLL_MDIV_192
AU_PLL_NDIV_192
AU_PLL_FRACL_176
AU_PLL_FRACH_176
AU_PLL_XDIV_176
AU_PLL_MDIV_176
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