STA310 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA310' PDF : 90 Pages View PDF
STA310
Address : 0x0E
Type: WO
Software Reset: NA
Hardware Reset: NA
Description:
Data can be fed into the STa310 by using this register
instead of the dedicated interface. there is no need to
byte align the bitstream when using this register.
9.5 PCM CONFIGURATION RESISTERS
PCMDIVIDER
Divider for PCM clock
7
6
5
4
3
2
1
0
Address : 0x54
Type: R/W
Software Reset: UND
Hardware Reset: UND
Description:
The PCM divider must be set according to the formu-
la below, where DAC_SCLK is the bit clock for the
DAC. When Div is set to 0, DAC_SCLK is equal to
DAC_PCMCLK:
Div = (DAC_PCMCLK/ (2 x DAC_SCLK)) -1
When the internal PLL is used, DAC_PCMCLK=384
x fs or 256 x fs. If DAC_PCMCLK = 384 x fs, the for-
mula becomes:
Div = (192 x Fs/DAC_SCLK) -1
If DAC_SCLK is 32 x Fs (common case with the 16
bit DAC), Div must be set to 5.
PCM divider value
5
3
Mode description
DAC_PCMCLK = 384Fs,
DAC is 16-bit mode
DAC_PCMLK = 256 Fs,
DAC is 16-bit mode
PCM divider value
2
1
Mode description
DAC_PCMLK = 384 Fs,
DAC is 32-bit mode
DAC_PCMLK = 256 Fs,
DAC is 32-bit mode
PCMCONF
PCM configuration
7
65 4
3
2
10
ODR DIF INV FOR SCL PREC[1:0]
Address: 0x55
Type: R/W
Software Reset: NC
Hardware Reset: UND
Description:
Bitfield
ORD
DIF
INV
FOR
SCL
PREC[1:0]
Description
PCM Order: This bit is significant only
when in 16-bit mode. When set, LSB
is sent first. When reset, MSB is sent
first.
PCM_DIFF: This bit is not significant
in 16-bit. When set, indicates that the
bits are not right-padded in the slot.
When reset, Ii is right padded.
INV_LRCLK: When set the polarty of
LRCLK is inverted: Left channel is
output when LRCLK is high.
When reset, the polarity of LRCLK is
such that the left channel is outout
when LRCLK is low.
FORMAT: This bit selects the data
output format: When set, the Sony
format is chosen. When reset 0 the
format is IS format.
INV_SCLK: When set, the polarity of
SCLK is inverted, the PCM outputs
and LRCLK will be stable for the
DACs on the falling edge of SCLK.
When reset, PCM outputs and LRCLK
are stable on the rising edge of SCLK.
PCM Precision
0: 16 bit mode (16 slots)
1: 18 bit mode (32 slots)
2: 20 bit mode (32 slots)
3: 24 bit mode (32 slots)
PCMCROSS
7
6
VCR
54
CLR[1:0]
3
2
CSW[1:0]
10
LRS[1:0]
40/90
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