STA321 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA321' PDF : 157 Pages View PDF
STA321
Digital processing stage
6.6
Biquads
The biquads are based on the following equation and is shown diagramatically in Figure 20.
Y[n] = b0 * X[n] + b1 * X[n-1] + b2 * X[n-2] - a1 * Y[n-1] - a2 * Y[n-2]
where Y[n] represents the output and X[n] represents the input. Fractional multipliers
are 24-bit signed with coefficient values in the range -1 (0xFFFFFF) to +1 (0x7FFFFF).
Figure 20. Biquad filter
b0/2
2
+
Z -1
b1/2
2
+
2
-a1/2
Z -1
Z -1
b2
+
-a2
Z -1
6.6.1
6.7
Presets
By default all the biquads values in RAM are set to give a bypass function; in actual fact, the
signal passes through unchanged. The coefficients for this are:
a1 / 2 = 0, a2 / 2 = 0, b0 / 2 = 0.5 (0x400000), b1 / 2 = 0, b2 / 2 = 0.
High-pass filter
The standard high-pass filter is provided by the STA321
Figure 21. High-pass filter frequency response
High Pass Filter
0
−5
−10
−15
−20
−25
−30
100
101
102
103
104
105
Freq. [Hz]
Doc ID 15351 Rev 3
39/157
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