STA538 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA538' PDF : 59 Pages View PDF
STA538
PLL
If register bit PLLCFG0.FRAC_CTRL = 0, then:
FVCO = FINFIN * LDF
FPHI = FVCO / ODF
In the above equations:
FRACT = Decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0]
IDF = Input division factor (refer to previous formulas)
LDF = Loop division factor (refer to previous formulas)
ODF = Output division factor = 2
FINFIN = INFIN frequency
FXTI = XTI frequency
FVCO = VCO frequency
FPHI = Frequency of the PLL output clock
When selecting the value of IDF, LDF and FRACT make sure the following limits are
maintained:
2.048 MHz < FXTI < 49.152 MHz
2.048 MHz < FINFIN < 16.384 MHz
65.536 MHz < FVCO < 98.304 MHz
There are also some additional constraints on IDF and LDF. IDF should be greater than 0,
LDF should be greater than 5 if FRAC_CTRL = 0 and greater than 8 if FRAC_CTRL = 1.
When automatic settings are not used, the PLL must be configured to generate an internal
frequency of N * Fs, where Fs is the LRCLKI pin frequency. Values of N are given in
Table 14.
Table 14. Oversampling table
Fs (kHz)
8
11.025
12
16
22.05
24
32
44.1
48
64
88.2
96
128
176.4
192
N
4096
4096
4096
2048
2048
2048
1024
1024
1024
512
512
512
256
256
256
FPHI (MHz)
32.768
45.1584
49.152
32.768
45.1584
49.152
32.768
45.1584
49.152
32.768
45.1584
49.152
32.768
45.1584
49.152
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