STCN75 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STCN75' PDF : 35 Pages View PDF
STCN75
Operation
2.5
Fault tolerance
For both comparator and interrupt modes, the alarm “fault tolerance” setting plays a role in
determining when the OS/INT output will be activated. Fault tolerance refers to the number
of consecutive times an error condition must be detected before the user is notified. Higher
fault tolerance settings can help eliminate false alarms caused by noise in the system. The
alarm fault tolerance is controlled by the bits (4 and 3) in the configuration register. These
bits can be used to set the fault tolerance to 1, 2, 4, or 6 as shown in Table 2. At power-up,
these bits both default to logic '0'.
Table 2.
FT1
0
0
1
1
Fault tolerance setting
FT0
STCN75 (consecutive faults)
Comments
0
1
Power-up default
1
2
0
4
1
6
Note:
OS output will be asserted one tCONV after fault tolerance is met, provided that the error
condition remains.
2.6
Shutdown mode
For power-sensitive applications, the STCN75 offers a low-power shutdown mode. The SD
bit in the configuration register controls shutdown mode. When SD is changed to logic '1,'
the conversion in progress will be completed and the result stored in the temperature
register, after which the STCN75 will go into a low-power standby state. The OS/INT output
will be cleared if the thermostat is operating in Interrupt mode and the OS/INT will remain
unchanged in comparator mode. The 2-wire interface remains operational in shutdown
mode, and writing a '0' to the SD bit returns the STCN75 to normal operation.
Doc ID 13307 Rev 9
13/36
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