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5.2 PCI Control/Status registers
Table 5. PCI Control/Status registers list
offset from base
address of CSR
Index
Name
00h
CSR0
PAR
08h
CSR1
TDR
10h
CSR2
RDR
18h
CSR3
RDB
20h
CSR4
TDB
28h
CSR5
SR
30h
CSR6
NAR
38h
CSR7
IER
40h
CSR8
LPC
48h
CSR9
SPR
50h
CSR10
---
58h
CSR11
TMR
60h
CSR12
---
68h
CSR13
WCSR
70h
CSR14
WPDR
78h
CSR15
WTMR
80h
CSR16
ACSR5
84h
CSR17
ACSR7
88h
CSR18
CR
8ch
CSR19
PCIC
90h
CSR20
PMCSR
94h
CSR21
---
98h
CSR22
---
9ch
CSR23
TXBR
a0h
CSR24
FROM
a4h
CSR25
PAR0
a8h
CSR26
PAR1
ach
CSR27
MAR0
b0h
CSR28
MAR1
Descriptions
PCI access register
transmit demand register
receive demand register
receive descriptor base address
transmit descriptor base address
status register
network access register
interrupt enable register
lost packet counter
serial port register
Reserved
Timer
Reserved
Wake-up Control/Status Register
Wake-up Pattern Data Register
watchdog timer
status register 2
interrupt enable register 2
command register
PCI bus performance counter
Power Management Command and Status
Reserved
Reserved
transmit burst counter/time-out register
flash(boot) ROM port
physical address register 0
physical address register 1
multicast address hash table register 0
multicast address hash table register 1
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