STE10 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STE10

PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY (5V)

STMicroelectronics 

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STE10/100

Table 10. Receive Descriptor Descriptions

Bit#

Name

Descriptions

24

RCH Second address chain

Used for chain structure, indicating the buffer 2 address is the next descriptor address. Ring

mode takes precedence over chained mode

23~22

--- reserved

21~11 RBS2 Buffer 2 size (DW boundary)

10~ 0 RBS1 Buffer 1 size (DW boundary)

RDES2

31~0

RBA1 Receive Buffer Address 1. This buffer address should be double word aligned.

RDES3

31~0

RBA2 Receive Buffer Address 2. This buffer address should be double word aligned.

5.4.2 Transmit Descriptor

Table 11. Transmit Descriptor Table

31

TDES0 Own

TDES1

Control

TDSE2

TDSE3

Note: 1. Descriptor addresses must be longword alignment

Status

Buffer2 byte-count

Buffer1 address

Buffer2 address

Table 12. Transmit Descriptor Descriptions

Bit#

Name

Descriptions

TDSE0

31

OWN Own bit

1: Indicates this descriptor is ready to transmit

0: No transmit data in this descriptor.

30-24

---

Reserved

23-22

UR Under-run count

21-16

---

Reserved

15

ES Error summary. Logical OR of the following bits:

1: under-run error

8: excessive collision

9: late collision

10: no carrier

11: loss carrier

14: jabber time-out

14

TO Transmit jabber time-out

0

Buffer1 byte-count

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